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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22001-1E
ASSP Communication Control
IEEE 1394 Bus Controller (for MPEG, DVC) MB86612
s DESCRIPTION
The MB86612 is 1394 serial bus controller exclusively for MPEG and DVC data transfer, compatible with the IEEE 1394 "FireWire" standard (IEEE Standard 1394-1995). Two built-in ports plus a differential transceiver and comparator are provided to enable formation of networks in a 1394 cable environment. The MB86612 supports s100 data transfer speeds. By integrating the physical layer and link layer on one chip, The MB86612 is designed to reduce mounting area as well as power consumption. The MB86612 has an exclusive data port for isochronous transfer, provides automatic packetizing and separation of header and data units, and is optimized for continuity of transfer processing. The MB86612 supports MPEG and DVC AV/C protocols, and includes the necessary built-in automatic operations and CSR's for providing the necessary operations for MPEG and DVC data transfer.
s FEATURES
* * * * * * * Compatible with IEEE 1394 high-performance serial bus standards Physical layer and link layer integrated on one chip 2 cable ports Supports s100 transfer speed (98.304 Mbit/sec) 3.3V single power supply operation Built-in PLL (for crystal oscillator) for internal clock signal generation Power saving modes 1) Forced sleep mode at instruction from MPU 2) Automatic sleep mode for non-connected ports * Header and data units automatically separated at receiving and automatic packetizing for sending * Supports cycle master functions (Continued)
s PACKAGES
100-pin plastic LQFP 120-pin plastic FBGA
(FPT-100P-M05)
(BGA-120P-M01)
MB86612
(Continued) * Built-in CSR's to provide isochronous resource manager functions * 32-bit CRC generation and check functions * General purpose port for asynchronous transfer and control (16-bit MPU bus) * Exclusive built-in ports for isochronous transfer (8-bit bus) * Built-in CRS's and automatic processes to support AV/C protocol (MPEG, DVC) 1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending. 2) Automatic generation of source packet headers (time stamp). 3) Source packet header (time stamp) match detection 4) DBC area automatic increment function 5) Empty packet sending and receiving 6) On-chip PCR (input/output 1 channel each) 7) Each CSR with automatic C&S lock processing and read processing 8) Automatic processing of late packet generation * Compatible with 4-core or 6-core cables * Packages: LQFP-100, FBGA-120
2
MB86612
s PIN ASSIGNMENTS
1. LQFP-100
100 MODE1
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
84 83 82 81 80 79 78 77 76
ID5 ID6 ID7 BUSRST PWR3 VSS VDD PWR2 PWR1
MODE0 LINKON TS IERR IV ILWRE IDIR ICLK VDD VSS ID0 ID1 ID2 ID3 ID4
RESET 1 INT VDD VSS ALE D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS D7 D6 AD5 AD4 AD3 AD2 AD1 D0 VDD VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 AVDD 74 AVSS 73 TPA0 72 TPB0 71 TPA0 70 TPB0 69 AVDD 68 AVSS 67 TPBIAS0 66 AVDD 65 AVSS 64 RO0 63 AVSS 62 AVDD 61 TPA1 60 TPB1 59 TPA1 58 TPB1 57 AVSS 56 AVDD 55 TPBIAS1 54 AVSS 53 AVDD 52 RO1 51 N.C.
WR (DS) 26
27 28 29 30 31 32 33 34 35 RD (R/W) VDD VSS CS A5 A4 A3 A2 A1
PMODE CTR OCLK VDD VSS X0 X1 TESTP AVSS AVDD VCOIN CHPO ROP AVSS AVDD
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3
MB86612
2. FBGA-120
13 N.C.
12 AVDD
11 AVSS
10 VCOIN
9 TESTP
8 XO
7 OCLK
6 PMODE
5 A3
4 A5
3 VDD
2 N.C. RD (R/W) N.C.
1 WR (DS) VSS N
N.C.
RO1
N.C. TPBIAS1 TPB1 N.C. AVSS AVSS
CHPO
AVSS
X1
VDD
CTR
A2
A4
VSS
M
AVDD
AVSS
ROP
AVDD
N.C.
VSS
N.C.
A1
N.C.
CS
VDD
L
AVSS TPA1 TPA1 N.C.
AVSS TPB1 AVDD RO0 TPBIAS0 AVDD TPB0 AVSS PWR2 N.C.
D0 AD3 D6 TOP VIEW VSS
AD1 AD4 N.C. VDD
AD2 AD5 D7 D8
K J I H
AVDD
N.C.
N.C.
D9
D10
G
AVSS TPA0 TPA0 AVDD PWR1
TPB0 N.C. PWR3 VSS VDD ID7 N.C. ID4 ID5 ID6 ID1 ID2 ID3 VSS ID0 N.C. IDIR ICLK VDD IV N.C. ILWRE LINKON TS IERR
D11 D13 ALE N.C.
D12 D14 VSS INT
N.C. D15 VDD N.C.
E D C B
BUSRST
MODE0 MODE1 RESET A
1 pin
4
MB86612
s PIN LIST
1. LQFP-100
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 I/O ID O -- -- ID ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O -- -- ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O -- -- ID ID -- -- ID ID ID ID ID -- ID -- Pin Name RESET INT VDD VSS ALE D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS D7 D6 AD5 AD4 AD3 AD2 AD1 D0 VDD VSS WR (XDS) WR (DS) RD (R/W) VDD VSS CS A5 A4 A3 VDD A2 VSS A1 NO. 36 34 37 35 38 36 39 37 40 38 41 39 42 40 43 41 44 42 45 43 46 44 47 45 48 46 49 47 50 48 51 49 52 50 53 51 54 52 55 53 56 54 57 55 58 56 59 57 60 58 61 59 62 60 63 61 64 62 65 63 66 64 67 65 68 66 69 57 70 58 I/O IU ID ID O IU O -- O -- O I/O -- -- I I/O -- -- I -- -- I -- O O I -- O -- O -- -- O -- -- O -- O -- -- O I/O -- I/O -- I/O I/O I/O -- I/O -- -- O -- -- O -- O -- -- I/O Pin Name PMODE A2 CTR A1 PMODE OCLK CTR VDD OCLK VSS VDD X0 VSS X1 TESTP X0 AVSS X1 TESTP AVDD VCOIN AVSS CHPO AVDD VCOIN ROP CHPO AVSS AVDD ROP AVSS N.C. AVDD RO1 AVDD N.C. AVSS RO1 TPBIAS1 AVDD AVDD AVSS TAPBIAS1 AVSS TPB1 AVDD TPA1 AVSS TPB1 TPA1 TPB1 AVDD TPA1 AVSS RO0 AVDD AVSS AVDD AVSS TPBIAS0 RO0 AVDD AVSS AVDD TPB0 TPB1
(Continued)
5
MB86612
(Continued)
NO. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 I/O I/O I/O I/O -- -- I I -- -- I I ID/O ID/O ID/O ID/O Pin Name TPA0 TPB0 TPA0 AVSS AVDD PWR1 PWR2 VDD VSS PWR3 BUSRST ID7 ID6 ID5 ID4 NO. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O ID/O ID/O ID/O ID/O -- -- ID ID O ID O ID/O O ID ID Pin Name ID3 ID2 ID1 ID0 VSS VDD ICLK IDIR ILWRE IV IERR TS LINKON MODE0 MODE1
6
MB86612
2. FBGA-120
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball No. A1 B1 B2 C1 C2 C3 D1 D2 D3 E1 E2 E3 F1 F2 F3 G1 G2 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 M1 N1 N2 M2 N3 M3 L3 I/O ID -- O -- -- ID ID/O ID/O ID/O -- ID/O ID/O ID/O ID/O -- ID/O -- -- ID/O -- ID/O ID/O ID/O ID/O ID/O ID/O ID/O -- -- -- ID -- ID -- -- ID Pin Name RESET N.C. INT VDD VSS ALE D15 D14 D13 N.C. D12 D11 D10 D9 N.C. D8 VDD VSS D7 N.C. D6 AD5 AD4 AD3 AD2 AD1 D0 VDD N.C. VSS WR (DS) N.C. RD (R/W) VDD VSS CS Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball No. N4 M4 L4 N5 M5 L5 N6 M6 L6 N7 M7 L7 N8 M8 L8 N9 M9 L9 N10 M10 L10 N11 M11 N12 N13 M13 M12 L13 L12 L11 K13 K12 K11 J13 J12 J11 I/O ID ID -- ID ID ID IU O -- O -- -- I/O I -- O -- -- I O O -- -- -- -- -- O -- -- O -- -- I/O I/O I/O -- Pin Name A5 A4 N.C. A3 A2 A1 PMODE CTR N.C. OCLK VDD VSS X0 X1 N.C. TESTP AVSS AVDD VCOIN CHPO ROP AVSS N.C. AVDD N.C. N.C. RO1 AVDD AVSS TPBIAS1 AVDD AVSS TPB1 TPA1 TPB1 N.C. Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Ball No. H13 H12 H11 G13 G12 G11 F13 F12 F11 E13 E12 E11 D13 D12 D11 C13 C12 B13 A13 A12 B12 A11 B11 C11 A10 B10 C10 A9 B9 C9 A8 B8 C8 A7 B7 C7 I/O I/O -- -- -- -- -- -- -- -- -- -- I/O I/O I/O -- I/O -- -- I -- I -- -- I I -- ID/O ID/O ID/O ID/O ID/O ID/O ID/O -- ID/O -- Pin Name TPA1 AVDD AVSS N.C. RO0 AVSS AVDD TPBIAS0 N.C. AVSS AVDD TPB0 TPA0 TPB0 N.C. TPA0 AVSS AVDD PWR1 N.C. PWR2 VDD VSS PWR3 BUSRST N.C. ID7 ID6 ID5 ID4 ID3 ID2 ID1 N.C. ID0 VSS
(Continued)
7
MB86612
(Continued)
Pin No. 109 110 111 112 Ball No. A6 B6 C6 A5 I/O -- ID ID O Pin Name VDD ICLK IDIR ILWRE Pin No. 113 114 115 116 Ball No. B5 C5 A4 B4 I/O -- ID O ID/O Pin Name N.C. IV IERR TS Pin No. 117 118 119 120 Ball No. C4 A3 B3 A2 I/O O ID -- ID Pin Name LINKON MODE0 N.C. MODE1
8
MB86612
s PIN DESCRIPTION
1. 1394 Interface
Pin name TPA0 TPA0 TPB0 TPB0 TPA1 TPA1 TPB1 TPB1 TPBIAS0 TPBIAS1 RO0 RO1 I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O Function Cable port 0 TPA positive signal I/O pin Cable port 0 TPA negative signal I/O pin Cable port 0 TPB positive signal I/O pin Cable port 0 TPB negative signal I/O pin Cable port 1 TPA positive signal I/O pin Cable port 1 TPA negative signal I/O pin Cable port 1 TPB positive signal I/O pin Cable port 1 TPB negative signal I/O pin Cable port 0 common voltage reference voltage output pin Cable port 1 common voltage reference voltage output pin Connect to GND through 4.7 k resistance Connect to GND through 4.7 k resistance
2. Isochronous-data Interface
Pin name ICLK I/O I Function Isochronous data interface CLK signal input pin (DC to 16 MHz). Note: When this clock is stopped, transfer is stopped. Also the "Data FIFO init (63h)" instruction (operand: 21) is invalid. Isochronous transfer sending/receiving switching signal input pin. 0 input: Clear ISO FIFO, go to sending mode. Sending starts after receiving 1 packet of data. 1 input: Clear ISO FIFO, go to receiving mode. If a `1' signal is entered during packet sending, receiving mode begins after sending of the current packet. The ILWRE signal is asserted after receiving 1 packet. Note: This signal should normally be left at `1', and switched to `0' only when sending. Isochronous FIFE access enable signal output pin. Sending: Asserted when 1 or more empty source packets are present in ISO FIFO. When negated, the data output up to the leading edge for the next ICLX. Receiving: Asserted when receiving of 1 source packet of data is completed. Negate conditions for this signal are determined by the ilwre-mode bit (bit 11) in the mode-control register. Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0) ID7 to ID0 enable signal input pin. Sending: While this signal is active, data from the ID7 to ID0 pins is loaded into ISO FIFO memory at the rising edge of the ICLK signal. Receiving: While this signal is active, data from ISO FIFO memory is sent to the ID7 to ID0 pins. Data is switched at the falling edge of the ICLK signal.
IDIR
I
ILWRE
O
ID7 to ID0
I/O
IV
I
(Continued)
9
MB86612
(Continued)
Pin name I/O Function Sending: DVC mode time stamp trigger signal input pin. (Input) The cycle timer value when this signal is asserted is added to the sending offset value and becomes the sending time stamp. Receiving: Time stamp match detect signal. (output) In MPEG mode, this signal is negative after reading 1 source packet of data. In DVC mode, this signal is asserted for the duration of 32 ticlk (32 periods of the ICLK signal). If an error is detected in a receiving isochronous packet this signal is not output. This signal is output when an error is detected in a receiving isochronous packet. When an error is detected the TS signal is not output, so that this signal should be used to trigger reading of the receiving packet. If an error such as causing discarding of received packets within a device, this signal is not output. This signal is output when the cycle timer value is changed. This signal may be output or not output, according to the CTR bit (bit 0) in the mode-control register. Cycle timer clock output (24.576 MHz). This signal may be output or not output, according to the CTR bit (bit 0) in the mode-control register.
TS
I/O
IERR
O
CTR
O
OCLK
O
3. System Interface
Pin name CS A5 to A1 D15 to D6, D0 AD5 to AD1 I/O I I I/O I/O Function Input pin for signals used by the MPU to select the MB86612 as an I/O device. Address input pins for internal register selection. Valid only in non-multiplexed mode. If multiplexed mode is selected these pins should be fixed at `0'. 16-bit data bus input/output pins (MSB is D15, LSB is D0). 16-bit data bus input/output pins (MSB is AD5, LSB is AD1). Used for address input signals when multiplexed mode is selected. 80-series mode: Read strobe signal input pin, used to output data from the MB86612 to the data bus. 68-series mode: Control signal input pin, used for data input/output operations to the MB86612. 80-series mode: Write strobe signal input pin, used to input data from the data bus to the MB86612. 68-series mode: DS signal input pin, output when data bus is enabled. ALE signal input pin, for signal output when addresses are enabled in multiplexed mode. In non-multiplexed mode, this signal should be fixed at `0'. Interrupt output pin.
RD (R/W)
I
WR (DS) ALE INT
I I O
10
MB86612
4. Other
Pin name X0 X1 VCOIN CHPO ROP RESET MODE0 MODE1 PMODE I/O I/O I I O O I I I I Function External crystal connection pins for oscillator circuits. VCO input pin for internal PLL. Charge pump output pin for internal PLL. Connect to GND through 4.7 k resistance. Reset signal input pin. This signal should be set to `0' when the system power supply is off. Input `0' for 80-series mode. Input `1' for 68-series mode. Input `0' for non-multiplexed mode. Input `1' for multiplexed mode. For cable power supply, set to `0' for power startup. Set to `1' when cable power supply is off or until system power is on. When operating from cable power supply, these pins determine the value of the `POWER_CLASS' area of Self-ID packets. When operating from system power supply, these pins correspond to the power bit in the Self-ID-PKT-param setting register. When the MB86612 is started from the power supply this bit determines whether a bus reset is applied automatically. Input `0' for no bus reset. Input `1' for bus reset. When this bit is set to `1', a bus reset is executed 200 s after the int-reset bit (bit 9) in the flag & status register (address 02h) is set to `1'. Link-on packet receiving detection pin. Outputs an `H' signal for 1 to 2 tclk (1 to 2 cycles of the crystal oscillator input signal) when a link-0n packet is received. When this signal is not used, leave it open. Analog power supply Analog ground Digital power supply Digital ground Test pin. Do not connect.
PWR1 to PWR3
I
BUSRST
I
LINKON AVDD AVSS VDD VSS TESTP
O -- -- -- -- --
11
MB86612
s BLOCK DIAGRAM
IDIR ICLK ISO sending/receiving FIFO (4kB) ILWRE Isochronous interface ID7 to ID0 IV TS IERR CTR OCLK ISO sending packet control TPA0 1394 interface (Port 0) TPA0 TPB0 TPB0 TPBIAS0
ISO receiving packet control LINK layer control circuit
PHY layer control circuit
TPA1 1394 interface (Port 1) TPA1 TPB1 TPB1 TPBIAS1
CS A5 to A1 System & asynchronous interface
ASYNC send-only FIFO (128 byte)
ASYNC sending packet processing
D15 to D6, D0 AD5 to AD1 RD (R/W) WR (DS) ALE INT
ASYNC receive-only FIFO (128 byte)
ASYNC receiving packet processing
Cycle mask
Transaction circuit block PLL circuit
Register block
CSR
12
MB86612
s BLOCK DESCRIPTIONS
* PHY Layer Control Circuit This block contains the IEEE 1394 physical layer control circuits. Both asynchronous transfer and isochronous transfer in a cable environment are supported. The transfer speed is 98.304 Mbit/sec. Two analog transceiver/receiver ports are built-in. This block provides bus status monitoring initialization operation after a bus reset is applied, as well as arbitration and encoding/decoding functions for data sending and receiving. * LINK Layer Control Circuit This block controls the generation and transfer of IEEE 1394 standard packets. 32-bit CRC generation and checking is performed for packet headers and data. A 32-bit cycle timer register is built-in to provide cycle master functions. * Sending/Receiving FIFO Contains built-in 4-byte FIFO areas, used for isochronous smoothing and rate conversion for both sending and receiving. Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer. * Packet Processing Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC. Receiving: Separates 1394 packet headers and data, strips CRC. * Special Transaction Circuits These circuits operate with the packet processing block in handling data from the isochronous interface, packetizing for MPEG and DVC transfer as well as rebuilding receiving data for the isochronous interface. * Register Block This block contains various device control registers, as well as registers for setting parameters required for 1394 transfer, AVC protocol registers and CSR. The built-in CSR provides isochronous resource manager functions. * PLL Circuit This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating clock and transfer clock signals. Reference oscillator frequency: 8.192 MHz.
13
MB86612
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage*1 Input voltage*1 Output voltage*1 Strage temperature Operating temperature* Output current* Overshoot*
4 4 3 2
Symbol VDD VI VO Tst Top IO -- --
Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 -40 -14 -- -- Max. 4.0 VDD + 0.5 VDD + 0.5 +125 +85 +14 VDD + 1.0 VSS - 1.0
Unit V V V C C mA V V
Undershoot* *1: *2: *3: *4:
Voltage values are based on Vss = 0 V. Not warranted for continuous operation. Normal output current flow (Minimum at Vo = 0 V, maximum at Vo = VDD). 50 ns or less.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage* "H" level input voltage "L" level input voltage Differential input voltage (for data transfer) Differential input voltage (for arbitration) Common mode input voltage Receiving input jitter Receiving input skew Output current Operating temperature * : Voltage values are based on Vss = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 14 CMOS input CMOS input Cable input Cable input Cable input Cable input Cable input CMOS output TPBIAS Symbol VDD VIH VIL VID VIDA VCM -- -- IOH/IOL Iot Ta Value Min. 3.0 VDD x 0.65 VSS 142 173 1.165 -- -- -4 -2 0 Max. 3.6 VDD VDD x 0.25 260 260 2.515 1.08 0.8 4 10 +70 Unit V V V mV mV V ns ns mA mA C
MB86612
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics 1.1 System Interface, etc
Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input pins Input leak current 3-state pin input Symbol VIH VIL VOH VOL ILI ILZ Rp IDDS0 IDDS1 IDDS2 IDDSS IDDCN IDDCR *1: Operating from system power supply *2: Operating from cable power supply VI = 0V to VDD VIH = VDD No port connected*1 1 port connected*1 2 ports connected*1 Forced sleep*1 Non repeating*2 Repeating*2 Conditions CMOS CMOS IOH = -4 mA IOL = -4 mA (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Unit Min. Typ. Max. VDD x 0.65 VSS VDD - 0.5 VSS -5 -5 25 -- -- -- -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- VDD VDD x 0.25 VDD 0.4 5 5 200 220 270 300 50 220 240 V V V V A A k mA mA mA mA mA mA
Input pull-up/pull down resistance
Power supply current
1.2 1394 Interface Driver
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Conditions Unit Min. Max. R1 = 56 Driver enabled Driver disabled -- 172 -0.81 -- 1.665 265 0.44 20 2.015 mV mA mV V
Parameter Differential output voltage Common phase current Off state voltage TPBIAS output voltage
Symbol VOD ICM VOFF VO
15
MB86612
1.3 1394 Interface - Comparator
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Conditions Unit Min. Max. Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled -20 168 -30 -- 0.6 -- 20 -- 30 -168 -- 1.0 A mV mV mV V V
Parameter Common phase input current Arbitration comparator "H" level threshold voltage Arbitration comparator "Z" level threshold voltage Arbitration comparator "L" level threshold voltage Port status comparator disconnection detect voltage Port status comparator connection detect voltage
Symbol IIC VSCH VSEZ VSCL VSD VSC
16
MB86612
2. AC Characteristics 2.1 System Clock
Parameter Clock frequency Clock cycle time Clock pulse width Clock rise/fall time Symbol fC tCLF tCLCH tCLCL tCR tCF Value Min. -- -- 50 -- Typ. 8.192 1/fc -- -- Max. -- -- -- 5 Unit MHz ns ns ns
tCLCH tCF 0. 65 VDD 0. 25 VDD
tCLF tCR
CLK
tCLCL
2.2 System Reset
Parameter Reset (RESET) "L" level pulse width Symbol tWRSL Value Min. 4 tclf Max. -- Unit ns
tWRSL
RESET
17
MB86612
2.3 Driver
Parameter Sending jitter Sending skew Sending rise time* Sending fall time* * : 10 to 90% value. Symbol tJT tSK tDR tDF Value Min. -- -- -- -- Max. 0.8 0.8 3.2 3.2 Unit ns ns ns ns
18
MB86612
2.4 System Interface
(1) 68-Series Register Write Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time Data setup time Data hold time R/W setup time R/W hold time ALE fall to DS fall time DS rise to ALE rise time ALE "H" level pulse width DS "L" level pulse width Symbol tAWSM tAWHM tCWSM tCWHM tDWSM tDWHM tRWSM tRWHM tDWD tLWD tALE tDSM Value Min. 10 5 10 5 10 0 5 5 10 5 10 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCWSM
tCWHM
CS
tRWSM tRWHM
R/W
tALE tDWD tLWD
ALE
tDSM
DS
tAWSM tAWHM tDWSM Data tDWHM
D15 to D6, D0 AD5 to AD1
Address
19
MB86612
(2) 68-System Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time Data output definition time Data output disabled time R/W setup time R/W hold time ALE fall to DS fall time DS rise to ALE rise time ALE "H" level pulse width DS "L" level pulse width Symbol tARSM tARHM tCRSM tCRHM tRLDM tRHDM tRWSM tRWH tDRD tLRD tALE tDSM Value Min. 10 5 10 5 -- 0 5 5 10 5 10 20 Max. -- -- -- -- 15 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCRSM
tCRHM
CS
tRWSM
tRWH
R/W
tLRD
tALE
tDRD
ALE
tDSM
DS
tARSM
tARHM
tRLDM
tRHDM Defined data
D15 to D6, D0 AD5 to AD1
Address
20
MB86612
(3) 68-Series Register Write Operation (non-multiplexed) Parameter Address setup time CS setup time CS hold time Data setup time Data hold time DS "L" level pulse width R/W setup time R/W hold time DS rise to address hold time Symbol tAWS tCWS tCWH tDWS tDWH tDS tRWS tRWH tAWH Value Min. 5 5 5 10 0 20 5 5 5 Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
tCWS
tCWH
CS
tRWS
tRWH
R/W
tDS
DS
tAWS tAWH Address
A5 to A0
tDWS
tDWH Data
D15 to D6, D0 AD5 to AD1
21
MB86612
(4) 68-Series Register Read Operation (non-multiplexed) Parameter Address setup time CS setup time CS hold time Data output definition time Data output disabled time DS "L" level pulse width R/W setup time R/W hold time Address hold time Symbol tARS tCRS tCRH tRLD tRHD tDS tRWS tRWH tARH Value Min. 5 5 5 -- 0 20 5 5 5 Max. -- -- -- 15 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
tCRS
tCRH
CS
tRWS
tRWH
R/W
tDS
DS
tARS tARH Address
A5 to A0
tRLD
tRHD Defined data
D15 to D6, D0 AD5 to AD1
22
MB86612
(5) 80-Series Register Write Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time Data setup time Data hold time ALE fall to WR fall time WR rise to ALE rise time ALE "H" level pulse width WR "L" level pulse width Symbol tAWSM tAWHM tCWSM tCWHM tDWSM tDWHM tDWD tLWD tALE tWRM Value Min. 10 5 10 5 10 0 10 5 10 20 Max. -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
tCWSM
tCWHM
CS
tALE
tDWD
tLWD
ALE
tWRM
WR
tAWSM
tAWHM
tDWSM Data
tDWHM
D15 to D6, D0 AD5 to AD1
Address
23
MB86612
(6) 80-Series Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time Data output definition time Data output disabled time ALE fall to RD fall time RD rise to ALE rise time ALE "H" level pulse width RD "L" level pulse width Symbol tARSM tARAHM tCRSM tCRHM tRLDM tRHDM tDRD tLRD tALE tRDM Value Min. 10 5 10 5 -- 0 10 5 10 20 Max. -- -- -- -- 15 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
tCRSM
tCRHM
CS
tALE
tDRD
tLRD
ALE
tRDM
RD
tARSM
tARAHM
tRLDM
tRHDM Defined data
D15 to D6, D0 AD5 to AD1
Address
24
MB86612
(7) 80-Series Register Write Operation (non-multiplexed) Parameter Address setup time CS setup time CS hold time Data setup time Data hold time WR "L" level pulse width Address hold time Symbol tAWS tCWS tCWH tDWS tDWH tWR tAWH Value Min. 5 5 5 10 0 20 5 Max. -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
tCWS
tCWH
CS
tWR
WR
tAWS tAWH
A5 to A0
Address
tDWS
tDWH Data
D15 to D6, D0 AD5 to AD1
25
MB86612
(8) 80-Series Register Read Operation (non-multiplexed) Parameter Address setup time CS setup time CS hold time Data output definition time Data output disabled time RD "L" level pulse width Address hold time Symbol tARS tCRS tCRH tRLD tRHD tRD tARH Value Min. 5 5 5 -- 0 20 5 Max. -- -- -- 15 -- -- -- Unit ns ns ns ns ns ns ns
tCRS
tCRH
CS
tRD
RD
tARS
tARH Address
A5 to 0
tRLD
tRHD Defined data
D15 to D6, D0 AD5 to AD1
26
MB86612
2.5 Isochronous Interface 2.5.1 ICLK
Parameter Clock frequency Clock cycle time Clock pulse width Clock rise/fall time Symbol -- tICLK tICLH tICLL tICR tICF Value Min. DC 62.5 10 -- Max. 16 -- 10 Unit MHz ns ns ns
tICLH tICF 0. 65 VDD 0. 25 VDD
tICLK tICR
ICLK
tICLL
27
MB86612
2.5.2 Sending Operation
(1) Start Sending Operation Parameter IDIR fall to ILWRE fall ICLK rise to ILWRE fall ILWRE fall to IV fall IV fall to ICLK rise Data setup time Data hold time TS input setup time* TS input hold time* Symbol tDLLL tCHLL tLLVL tVLCH tIDS tIDH tTSS tTSH Value Min. -- -- 1 ticlk + 10 20 20 0 20 20 Max. 4 ticlk + 10 40 -- -- -- -- 1 ticlk - 10 1 ticlk - 10 Unit ns ns ns ns ns ns ns ns
ICLK
IDIR
tCHLL tDLLL
ILWRE
tLLVL tVLCH
IV
tTSS tTSH
TS
tIDS
tIDH 2 3
ID7 to ID0
1
* : Specifications tIDH and tTSS are valid in DVC mode only. TS input is not used in MPEG mode.
28
MB86612
(2) End Sending Operation Parameter ICLK rise to ILWRE rise ILWRE rise to IV rise ILWR negate time* Symbol tCHLH tLHVH tLWH Value Min. -- 1 ticlk + 10 2 ticlk - 10 Max. 40 -- -- Unit ns ns ns
ICLK
IDIR
tCHLH
tLWH
ILWRE
tLHVH
IV
ID7 to ID0
N-2
N-1
N
1
* : The MB86612 operates in `negate mode', in which the ILWRE signal is negated for each source packet received, as well as `assert mode', in which the ILWRE signal is continuously asserted as long as ISO sending and receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled.
29
MB86612
(3) IV Temporary Negation in Sending Operation Parameter ICLK rise to IV rise Date setup time Data hold time Symbol tCHVH tIDS tIDH Value Min. 0 20 0 Max. 1 ticlk - 20 -- -- Unit ns ns ns
ICLK
IDIR
ILWRE
tCHVH
IV
tIDS tIDH N N+1
ID7 to ID0
N-1
30
MB86612
2.5.3 Receiving Operation
(1) Start Receiving Operation Parameter ICLK rise to ILWRE fall ILWRE fall to IERR fall* ILWRE fall to IV fall IV fall to ICLK rise Data output definition time Data output disable time TS output assert time*2
1
Symbol tCHLL tLLEL tLLVL tVLCH tVLIDV tCLIDX tTSWL
Value Min. -- -- 1 ticlk + 10 20 -- 0 32 ticlk - 10 Max. 40 1 ticlk + 10 -- -- 20 10 --
Unit ns ns ns ns ns ns ns
ICLK
IDIR
tCHLL
ILWRE
tLLEL
IERR
tTSWL
TS*
3
tLLVL
tVLCH
IV
tVLIDV tCLIDX 1 2
ID7 to ID0
Hi - Z
*1: The IERR signal is output when an error is detected in receiving data. *2: Specification tD is valid only in DVC mode. It does not apply to MPEG mode. *3: The TS signal is output in synchronization with the rise of the ICLK pulse at the time the receiving packet time stamp match is detected. 31
MB86612
(2) End Receiving Operation Parameter ICLK rise to ILWRE rise ILWRE rise to IV rise Final data output disable time ILWRE negate time*
1
Symbol tCHLH tLHVH tVHIDX tLWH
Value Min. -- 1 ticlk + 10 -- 2 ticlk - 10 Max. 40 -- 20 --
Unit ns ns ns ns
ICLK
IDIR
tCHLH tLWH
ILWRE
IERR*
2
TS*
2
tLHVH
IV
tVHIDX
ID7 to ID0
N-2
N-1
N
Hi - Z
*1: The MB86612 operates in `negate mode', in which the ILWRE signal is negated for each source packet received, as well as `assert mode', in which the ILWRE signal is continuously asserted as long as ISO sending and receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled. *2: The TS (in MPEG mode) and IERR signals are negated in synchronization with the ILWRE signal.
32
MB86612
(3) IV Temporary Negation in Receiving Operation Parameter IV rise to ICLK rise Symbol tVHCH Value Min. 40 Max. -- Unit ns
ICLK
IDIR
ILWRE
tVHCH
IV
ID7 to ID0
N-1
N
Hi - Z
N+1
33
MB86612
s INTERNAL REGISTERS
The MB86612 internal registers have 3-bank construction, with 16-bit access to all registers. Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary for AV/C (MPEG, DVC) operation, and bank 2 contains CSR's. In addition each bank has registers used in common for MB86612 device control.
1. Bank Common Registers
The following registers can be accessed in any bank from bank 0 to bank 2. Address HEX 00 02 04 06 08 0A 0C 0E 3E A5 0 0 0 0 0 0 0 0 1 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 1 A2 0 0 1 1 0 0 1 1 1 A1 0 1 0 1 0 1 0 1 1 Write operation mode-control register (reserved) instruction fetch register interrupt mask register (reserved) ASYNC data port (sending) (reserved) (reserved) bank select register Read operation flag & status register interrupt code register Receiving acknowledge display register ASYNC data port (receiving)
34
MB86612
2. Bank 0 Registers
Bank 0 contains the registers required for 1394 settings and transfers. Access to this bank is enabled by writing `0000h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation Sending ISO PKT header setting register (high) Sending ISO PKT header setting register (low) Sending ASYNC des ID setting register Sending ASYNC PKT param setting register Sending ASYNC data length setting register Sending ASYNC ex tcode setting register Sending ASYNC source ID setting register Sending ASYNC resp param setting register Sending ASYNC des offset setting register (high) Sending ASYNC des offset setting register (middle) Sending ASYNC des offset setting register (low) (reserved) (reserved) (reserved) (reserved) (reserved) state clear setting register Self ID PKT param setting register (reserved) (reserved) (reserved) (reserved) (reserved) Read operation Receiving ISO PKT header display register (high) Receiving ISO PKT header display register (low) (reserved) Receiving ASYNC PKT param display register Receiving ASYNC data length display register Receiving ASYNC ex tcode display register Receiving ASYNC source ID display register Receiving ASYNC resp param display register Receiving ASYNC des offset display register (high) Receiving ASYNC des offset display register (middle) Receiving ASYNC des offset display register (low) PHY ID display register NODE config display register PORT config display register (port0) PORT config display register (port1) root ID display register ISO resource manager ID display register cycle timer monitor display register (high) cycle timer monitor display register (low)
35
MB86612
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (MPEG, DVC) protocols. Access to this bank is enabled by writing `0001h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation Sending time stamp offset setting register Sending time stamp offset setting register Sending CIP header setting register (highest) Sending CIP header setting register (high) Sending CIP header setting register (low) Sending CIP header setting register (lowest) OMPR (high) OMPR (low) OPCR0 (high) OPCR0 (low) (reserved) (reserved) (reserved) (reserved) IMPR (high) IMPR (low) IPCR0 (high) IPCR0 (low) (reserved) (reserved) (reserved) (reserved) AV mode setting register Read operation Receiving time stamp display register (high) Receiving time stamp display register (low) Receiving CIP header display register (highest) Receiving CIP header display register (high) Receiving CIP header display register (low) Receiving CIP header display register (lowest) AV status register
36
MB86612
4. Bank 2 Registers
Bank 2 contains CSR's. Access to this bank is enabled by writing `0002h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation bus manager ID register (high) bus manager ID register (low) bandwidth available register (high) bandwidth available register (low) channels available high register (high) channels available high register (low) channels available low register (high) channels available low register (low) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) Read operation
37
MB86612
s ORDERING INFORMATION
Partnumber MB86612PFV MB86612PBT Package 100-pin plastic LQFP (FPT-100P-M05) 120-pin plastic FBGA (BGA-120P-M01) Remarks
38
MB86612
s PACKAGE DIMENSIONS
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 +.008 .059 -.004
+0.20
(Mounting height)
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
120-pin plastic FBGA (BGA-120P-M01)
12.000.10(.472.004)SQ 1.25 -0.10 .049 -.004 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.20 +.008
9.60(.378)REF 0.80(.031)TYP
13 12 11 10 9 8 7 6 0.10(.004) 5 4 INDEX 3 2 1 NMLKJHGFEDCBA C0.80(.031) 120-O0.450.10 (120-O.018.004) 0.08(.003)
M
C
1998 FUJITSU LIMITED B120001S-1C-1
Dimensions in mm (inches)
39
MB86612
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901 (c) FUJITSU LIMITED Printed in Japan
40

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